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sy89112u 2.5/3.3v low - jitter, low - skew 1:12 lvpecl fanout buffer with 2:1 input mux and internal termination precision edge is a regi stered trademark of micrel, inc micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com july 2010 m9999 -072809 -d hbwhelp@micrel.com or (408) 955 - 1690 general description the sy89112u is a low - jitter, low - skew, high - speed lvpecl 1:12 differential fanout buffer o p timized for precision telecom and enterprise server distribution applications. the input includes a 2:1 mux for clock switchover application . unlike other multiplexers, this input includes a unique isolation design to minimize channel - to - channel crosstalk. the sy89112u distributes clock fr e quencies from dc to >2ghz guaranteed over temperature and voltage. the sy89112u incorporates a synchronou s ou t put enable (en) so that the outputs will only be e n abled/disabled when they are already in the low state. this reduces the chance of generating ?runt? clock pulses. the sy89112u differential input includes micrel?s unique, patent - pending 3 - pin input t ermination architecture that directly interfaces to any di f ferential signal (ac - or dc - coupled) as small as 100mv (200mv pp ) without any level shifting or termination resistor networks in the signal path. for ac - coupled input interface, an on - board output r eference voltage (vref - ac) is provided to bias the center - tap (vt) pin. the outputs are 800mv, 100k - compat i ble lvpecl with fast rise/fall times guaranteed to be less than 220ps. the sy89112u operates from a 2.5v 5% or 3.3v 10% supply and is guaranteed ov er the full industrial temper a ture range of ? 40c to +85c. the sy89112u is part of micrel?s high - speed, precision edge ? product line. all support documentation can be found on m i crel?s web site at www.micrel.com . precision edge ? features ? selects between 1 of 2 inputs, and provides 12 prec i sion, low skew lvpecl output copies ? guaranteed ac performance over temperature and voltage: ? dc to >2ghz throughput ? <550ps propagation delay clk - to - q ? <220ps rise/fall time ? <25ps output - to - output skew ? ultra - low jitter design: ? 109f s rms phase jitter (typ.) ? <0.7ps rms crosstalk induced jitter ? unique, patent - pending input termination and vt pin accepts dc - coupled and ac - coupled differential inputs ? unique, patent - pending 2:1 input mux provides superior isolation to minimize channel - to - channel crosstalk ? 800mv, 100k lvpecl output swing ? power supply 2.5v + 5% or 3.3v + 10% ? ? industrial temperature range ? 40c to +85c ? ? available in 44 - pin (7mm x 7mm) qfn package applications ? multi - pro cessor server ? sonet/sdh clock/data distribution ? fibre channel distribution ? gigabit ethernet clock distribution
micrel, inc. sy89112u july 2010 2 m9999 -072809 -d hbwhelp@micrel.com or (408) 955 - 1690 functional block diagram
micrel, inc. sy89112u july 2010 3 m9999 -072809 -d hbwhelp@micrel.com or (408) 955 - 1690 ordering information part number package type operating range package marking lead finish SY89112UMI qfn -44 i ndu s trial sy89112u sn -pb SY89112UMItr (2) qfn -44 indu s trial sy89112u sn -pb sy89112umy qfn -44 indu s trial sy89112u with pb - free bar - line indicator matte -sn pb - free sy89112umytr (2) qfn -44 indu s trial sy89112u with pb - free bar - line indicator matte -sn pb - fre e notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. pin configuration 44- pin qfn
micrel, inc. sy89112u july 2010 4 m9999 -072809 -d hbwhelp@micrel.com or (408) 955 - 1690 pin description pin number pin name pin function 2, 5 7, 10 clk0, /clk0 clk1, /clk1 differential inp uts: these input pairs are the differential signal inputs to the device. i n puts accept ac - or dc - coupled differential signals as small as 100mv. each pin of a pair internally terminates to a vt pin through 50 ? . note that these inputs will default to an ind eterm i nate state if left open. please refer to the ?input interface applications? section for more details. 3, 8 vt0, vt1 input termination center - tap: each side of the differential input pair terminates to a vt pin. the vt pins provide a center - tap to a termination network for maximum interface flexibility. see ?input interface applications? section for more details. 4, 9 vref - ac0 vref - ac1 reference voltage: these outputs bias to v cc ? 1.2v. they are used when ac coupling the inputs (clk, /clk). for ac - coupled applications, connect v ref - ac to the vt pin and bypass with a 0.01 f low esr capacitor to v cc . see ?input inte r face applications? section for more details. maximum sink/source current is 1.5ma. due to the limited drive capability, each vref - ac pi n is only intended to drive its respective vt pin. 44 clk_sel this single - ended ttl/cmos - compatible input selects the inputs to the multiplexer. note that this input is internally connected to a 25k ? pull - up resistor and will default to a logic high state if left open. 12 en this single - ended ttl/cmos - compatible input functions as a synchronous output enable. the synchronous enable ensures that enable/disable will only occur when the outputs are in a logic low state. note that this input is internally con nected to a 25k ? pull - up resistor and will d e fault to logic high state (enabled) if left open. 13,22,23,28, 33,34,43 vcc positive power supply. bypass with 0.1 f//0.01 f low esr capacitors and place as close to each vcc pin as possible. 42, 41 40, 39 38, 37 36, 35 32, 31 30, 29 27, 26 25, 24 21, 20 19, 18 17, 16 15, 14 q0, /q0 q1, /q1 q2, /q2 q3, /q3 q4, /q4 q5, /q5 q6, /q6 q7, /q7 q8, /q8 q9, /q9 q10, /q10 q11, /q11 differential 100k lvpecl outputs: these lvpecl outputs are the precision, low skew copies of the inputs. please refer to the truth table below for details. u n used output pairs may be left open. terminate with 50 ? to v cc ? 2v. see ?lvpecl output interface applications? section for more details. 1, 6, 11 gnd, exposed pad ground. gnd pins and exposed pad must both be connected to the most negative potential of chip the ground. truth table en clk_sel q /q h l clk0 /clk0 h h clk1 /clk1 l x l (1) h (1) notes: 1. transition occurs on next negative transition of the non - inverted input.
micrel, inc. sy89112u july 2010 5 m9999 -072809 -d hbwhelp@micrel.com or (408) 955 - 1690 absolute maximum ratings (1) supply voltage (v cc ) .................................... ? 0.5v to + 4.0v input voltage (v in ) .......................................... ? 0 .5v to vcc lvpecl output current (i out ) continuous ............................................................ 50ma surge .................................................................. 100ma termination current source or sink current on vt ............................ 100ma input current source or sink current on clk, /clk ................. 50ma v ref-ac current source or sink current ........................................... 2ma lead temperature (soldering, 20s ec) ...................... + 260 c storage temperature (ts) ........................ ? 65 c to + 150 c operating rating(2) supply voltage (v cc ) ......................... + 2.375v to + 2.625v + 3.0v to + 3.6v ambient temperature (t a ) ....................... ? 40 c to + 85 c package thermal resistance (3) qfn ( ja ) still - air ...................................................... 42 c/w qfn ( jb ) junction - to - board .................................... 20 c/w dc electrical characteristics (4) t a = ? 40c to +85c, unless otherwise stated. symbol parameter condition min . typ . max . units v cc power supply 2.375 3.0 2.625 3.6 v v i cc power supply current no load, max. v cc 95 130 ma r in input resistance (in -to - vt) 45 50 55 ? r diff_in differential input resistance (in -to - /in) 90 100 110 ? v ih input high voltage (in, /in) 1.2 v cc v v il input low voltage (in, /in) 0 v ih ? 0.1 v v in input voltage swing (in, /in) see figure 1a. 0.1 1.7 v v diff_in differential input voltage swing |in ? /in| see figure 1b. 0.2 v v t_in in -to -vt (in, /in) 1.28 v v ref - ac output reference voltage v cc ? 1.3 v cc ? 1.2 v cc ? 1.1 v notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this i s a stress rating only and fun c tional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. the d ata sheet limits are not guaranteed if the device is operated beyond the operating ratings 3. package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the pcb. ja and jb values are determined for a 4 - layer board in still - air, unless otherwise stated. 4. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established .
micrel, inc. sy89112u july 2010 6 m9999 -072809 -d hbwhelp@micrel.com or (408) 955 - 1690 lvpecl outputs dc electrical characteristics (5) v cc = +2.5v 5% or +3.3v 10%; t a = ? 40c to +85c; r l = 50 ? to v cc ? 2v, unless otherwise stated. symbol parameter condition min . typ . max . units v oh output high voltage ( q, /q ) v cc ? 1.145 v cc ? 0.895 v v ol output low voltage ( q, /q ) v cc ? 1.945 v cc ? 1.695 v v out output voltage swing ( q, /q ) see fig ure 1a 550 800 mv v diff - out di fferential output voltage swing ( q, /q ) see figure 1b 1100 1600 mv lvttl/cmos dc electrical characteristics (5) v cc = +2.5v 5% or +3.3v 10%; t a = ? 40c to +85c, unless otherwise stated. symbol parameter condition min . typ . max . units v ih input high voltage 2.0 v cc v v il input low voltage 0.8 v i ih input high current ? 125 30 a i il input low current ? 300 a note: 5. the circuit is designed to meet the dc specifications shown in the above table after thermal e quilibrium has been established .
micrel, inc. sy89112u july 2010 7 m9999 -072809 -d hbwhelp@micrel.com or (408) 955 - 1690 ac electrical characteristics (6) v cc = +2.5v 5% or +3.3v 10%; t a = ? 40c to + 85c, r l = 50 ? to v cc ? 2v, unless otherwise stated. symbol parameter condition min. typ. max. units f max maximum operating frequency v out 400mv 2 3 ghz t pd propagation delay clk to q v in 100mv 300 400 550 ps propagation delay clk_sel to q 200 350 600 ps t pd tempco differential propagation delay te m perature coefficient 150 fs/ o c t s set - up time en -to - clk note 7 0 ps t h hold time clk - to -en note 7 500 ps t skew output -to - output skew part -to - part skew note 8 note 9 25 200 ps t jitter rms phase jitter output = 622mhz, integration range: 12khz ? 20mhz 109 fs rms adjacent channel crosstalk - induced jitter note 10 0.7 ps (rms) t r, t f output rise/fall time (20% to 80%) at full output swing. 70 140 220 ps notes: 6. high - frequency ac - parameters are guaranteed by design and characterization. 7. set - up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. for asynchrono us applications, set - up and hold do no t apply. 8. output - to - output skew is measured between two different outputs under identical input transitions. 9. part - to - part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respect ive inputs . 10. crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with r e spect to each other at the inputs.
micrel, inc. sy89112u july 2010 8 m9999 -072809 -d hbwhelp@micrel.com or (408) 955 - 1690 phase noise characteristics v cc = +3.3v, gnd = 0, v in = 100mv, r l = 50 ? to v cc ? 2v, t a = 25c, unless otherwise stated.
micrel, inc. sy89112u july 2010 9 m9999 -072809 -d hbwhelp@micrel.com or (408) 955 - 1690 operating characteristics v cc = +3.3v, gnd = 0, v in = 100mv, r l = 50 ? to v cc ? 2v, t a = 25c, unless otherwise stated.
micrel, inc. sy89112u july 2010 10 m9999 -072809 -d hbwhelp@micrel.com or (408) 955 - 1690 functional characteristics v cc = +3.3v, gnd = 0, v in = 100mv, r l = 50 ? to v cc ? 2v, t a = 25 c, unless otherwise stated.
micrel, inc. sy89112u july 2010 11 m9999 -072809 -d hbwhelp@micrel.com or (408) 955 - 1690 single- ended and differential swings figure 1a. single - ended voltage swing figure 1b. differential voltage swing timing diagrams t pd ? differential in -to - differential out t pd ? clk_sel -to - differential out t pd ? set - up and hold time en -to - differential out
micrel, inc. sy89112u july 2010 12 m9999 -072809 -d hbwhelp@micrel.com or (408) 955 - 1690 input and output stages figure 2a. simplified differential input stage figure 2b. simplified lvpecl output stage input interface applications figure 3a. lvp ecl interface (dc - coupled) figure 3b. lvpecl interface (ac - coupled) figure 3c. cml interface (dc - coupled) figure 3d. cml interface (ac - coupled) figure 3e. lvds interface
micrel, inc. sy89112u july 2010 1 3 m9999 -072809 -d hbwhelp@micrel.com or (408) 955 - 1690 lvpecl output interface applications lvpecl has high - input impeda nce, very - low output (open emitter) impedance, and small signal swing, which result in low emi. lvpecl is ideal for driving 50 ? and 100 ? controlled impedance transmission lines. there are several techniques for terminating the lvpecl output: parallel termination - thevenin equivalent, parallel termination (3 - resistor), and ac - coupled termination. unused output pairs may be left flo ating. however, single - ended outputs must be terminated or balanced. figure 4a. parallel thevenin - equivalent termination figure 4b. parallel termination (3 - resistor) related product and support documentation part number function data s heet link sy89113u 2.5v/3.3v low - jitter, low - skew, 1:12 lvds fanout buffer with 2:1 input mux and internal termination www.micrel.com/product - info/products/sy89113u.shtml hbw solutio ns new products and applications www.micrel.com/product - info/products/solutions.shtml
micrel, inc. sy89112u july 2010 14 m9999 -072809 -d hbwhelp@micrel.com or (408) 955 - 1690 package information 44- pin qfn micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http://www.micrel.c om the information furnished by micrel in this data sheet is believed to be accurate and reliable. however, no responsibility is assumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notifica tion to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where mal function of a product can reasonably be expected to result in personal injury. life support devices or syste ms are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a signific ant injury to the user. a purchaser?s use or sale of micrel pr oducts for use in life support appliances, devices or systems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 200 5 micrel, incorporated.

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